msm: clk: qcom: fix recalc rate callback for 10nm DSI PLL

Recalculate the DSI PLL VCO clock rate from the registers only
for the handoff usecases. This is due to the fact that the rate
calculation requires the knowledge of PLL out_div divider clock
rate which is only set after the VCO rate is set. This will
ensure that stale values are not used in VCO rate recalculation.

Change-Id: I690fba18ba59b9912c0bfe7284bfed793fd04cd3
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>