soc: qcom: glink_spi_xprt: Remove extra SPI transactions

The TX FIFO write reg and the RX FIFO read reg are controlled
by this processor. Keep track of the state of these two indexes
to reduce the amount of SPI reads.

CRs-Fixed: 2093123
Change-Id: I4ffa0e08bce6dabd57f33a13fef8107211ce3f09
Signed-off-by: Chris Lew <clew@codeaurora.org>