msm_11ad: 11AD SMMU changes to allow enabling of SMMU stage1

Add the following changes to support enabling of SMMU stage1:
- Enable DMA coherency and PAGE_TABLE_FORCE_COHERENT attr
to allow cache coherency when SMMU stage1 is enabled
- Add the option to define SMMU base address and size in DT
- Add DT node flag to determine if stage1 is enabled

Change-Id: I38b0ee3d5c4bf533f91077ee69bd464dfdd358c8
Signed-off-by: Maya Erez <merez@codeaurora.org>