msm: kgsl: Use fence mechanism for A6XX preemption register writes

This is an alternative method for successfully writing to preemption
registers if device is in IFPC. The A6XX preemption registers are
fenced. That means, when we write to these registers and if the device
is in IFPC, we can poll the fence status register to make sure the GPU
is up and write went through. The preemption registers are saved/restored
across IFPC. This ensures that if device goes to IFPC during one of
these register writes, the writes will not be lost.

Change-Id: Id09ec236b19da1491a588bfe063cfed220ffaf62
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>