ASoC: msm_sdw: Move the delay logic inside bulk write loop

On consecutive writes in bulk write API, ensure delay
is provided for atleast 100us between each soundwire
master write for WR_DONE status update and reflect
current register value. Also ensure delay in soundwire
master read is present after register address update
and before register value read.

CRs-Fixed: 2035787
Change-Id: I8399c5ca32328abdd4e90b46d6f8d6a6c0225905
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>