Skip to content
Commit 4e68f5a7 authored by Rajendra Nayak's avatar Rajendra Nayak Committed by Paul Walmsley
Browse files

ARM: OMAP3: Fix CM register bit masks 



The register bits for MPU_CLK_SRC and IVA2_CLK_SRC in CM_CLKSEL1_PLL
register are 3 bits wide.  Fix the MASK definition accordingly.

Signed-off-by: default avatarRajendra Nayak <rnayak@ti.com>
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent 96566043
Hide whitespace changes
Inline Side-by-side
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment