clk: mdss: adjust PLL disable sequence to avoid glitch

Adjust the PLL disable sequence as per the latest HW
programming guidelines to ensure there will not be any
stray clock glitches when PLL is turned OFF abruptly.

Change-Id: I3636d09df4e86601e8b5189db1ad088a66f83489
Signed-off-by: Vara Reddy <varar@codeaurora.org>