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Commit c8d09530 authored by Vara Reddy's avatar Vara Reddy
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clk: mdss: adjust PLL disable sequence to avoid glitch 



Adjust the PLL disable sequence as per the latest HW
programming guidelines to ensure there will not be any
stray clock glitches when PLL is turned OFF abruptly.

Change-Id: I3636d09df4e86601e8b5189db1ad088a66f83489
Signed-off-by: default avatarVara Reddy <varar@codeaurora.org>
parent 6d6d60c0
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